Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

Off-chip buses account for a significant portion of the total system power consumed in embedded systems. Bus encoding schemes have been proposed to minimize power dissipation, but none has been demonstrated to be optimal with respect to any measure. In this paper, we give the first provably optimal and explicit (polynomial-time constructible) families of memoryless codes for minimizing bit transitions in off-chip buses. Our results imply that having access to a clock does not make a memoryless encoding scheme that minimizes bit transitions more powerful.Comment: Proceedings of the 2006 IEEE/ACM international Conference on Computer-Aided Design (San Jose, California, November 05 - 09, 2006). ICCAD '06. ACM, New York, NY, 369-37

Locating one pairwise interaction: Three recursive constructions

In a complex component-based system, choices (levels) for components (factors) may interact to cause faults in the system behaviour. When faults may be caused by interactions among few factors at specific levels, covering arrays provide a combinatorial test suite for discovering the presence of faults. While well studied, covering arrays do not enable one to determine the specific levels of factors causing the faults; locating arrays ensure that the results from test suite execution suffice to determine the precise levels and factors causing faults, when the number of such causes is small. Constructions for locating arrays are at present limited to heuristic computational methods and quite specific direct constructions. In this paper three recursive constructions are developed for locating arrays to locate one pairwise interaction causing a fault